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Erik Tylek Kettenburg
114
digistump-sam/system/CMSIS/Device/ARM/ARMCM4/Include/ARMCM4.h
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114
digistump-sam/system/CMSIS/Device/ARM/ARMCM4/Include/ARMCM4.h
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/**************************************************************************//**
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* @file ARMCM4.h
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* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
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* for CM4 Device Series
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* @version V1.05
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* @date 26. July 2011
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*
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* @note
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* Copyright (C) 2010-2011 ARM Limited. All rights reserved.
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*
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* @par
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* ARM Limited (ARM) is supplying this software for use with Cortex-M
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* processor based microcontrollers. This file can be freely distributed
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* within development tools that are supporting such ARM based processors.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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******************************************************************************/
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#ifndef ARMCM4_H
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#define ARMCM4_H
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/*
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* ==========================================================================
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* ---------- Interrupt Number Definition -----------------------------------
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* ==========================================================================
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*/
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typedef enum IRQn
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{
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/****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
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NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
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HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
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MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
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BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
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SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
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DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
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/****** ARMCM4 specific Interrupt Numbers ********************************************************/
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GPIO_IRQn = 0 /*!< GPIO Interrupt */
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} IRQn_Type;
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/*
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* ==========================================================================
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* ----------- Processor and Core Peripheral Section ------------------------
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* ==========================================================================
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*/
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/* Configuration of the Cortex-M4 Processor and Core Peripherals */
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#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
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#define __MPU_PRESENT 1 /*!< MPU present or not */
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#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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#define __FPU_PRESENT 1 /*!< FPU present or not */
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#include <core_cm4.h> /* Cortex-M4 processor and core peripherals */
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#include "system_ARMCM4.h" /* System Header */
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/******************************************************************************/
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/* Device Specific Peripheral registers structures */
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/******************************************************************************/
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/*--------------------- General Purpose Input and Ouptut ---------------------*/
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typedef union
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{
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__IO uint32_t WORD;
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__IO uint8_t BYTE[4];
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} GPIO_Data_TypeDef;
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typedef struct
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{
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GPIO_Data_TypeDef DATA [256];
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__O uint32_t DIR;
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uint32_t RESERVED[3];
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__O uint32_t IE;
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} ARM_GPIO_TypeDef;
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/******************************************************************************/
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/* Peripheral memory map */
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/******************************************************************************/
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/* Peripheral and SRAM base address */
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#define ARM_SRAM_BASE (( uint32_t)0x20000000UL)
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#define ARM_PERIPH_BASE (( uint32_t)0x40000000UL)
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/* Peripheral memory map */
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#define ARM_GPIO_BASE ARM_PERIPH_BASE
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#define ARM_GPIO0_BASE (ARM_GPIO_BASE)
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#define ARM_GPIO1_BASE (ARM_GPIO_BASE + 0x0800UL)
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#define ARM_GPIO2_BASE (ARM_GPIO_BASE + 0x1000UL)
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/******************************************************************************/
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/* Peripheral declaration */
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/******************************************************************************/
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#define ARM_GPIO0 ((ARM_GPIO_TypeDef *) ARM_GPIO0_BASE)
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#define ARM_GPIO1 ((ARM_GPIO_TypeDef *) ARM_GPIO1_BASE)
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#define ARM_GPIO2 ((ARM_GPIO_TypeDef *) ARM_GPIO2_BASE)
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#endif /* ARMCM4_H */
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@@ -0,0 +1,62 @@
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/**************************************************************************//**
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* @file system_ARMCM4.h
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* @brief CMSIS Cortex-M4 Device System Header File
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* for CM4 Device Series
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* @version V1.05
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* @date 19. July 2011
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*
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* @note
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* Copyright (C) 2010-2011 ARM Limited. All rights reserved.
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*
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* @par
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* ARM Limited (ARM) is supplying this software for use with Cortex-M
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* processor based microcontrollers. This file can be freely distributed
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* within development tools that are supporting such ARM based processors.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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******************************************************************************/
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#ifndef SYSTEM_ARMCM4_H
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#define SYSTEM_ARMCM4_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
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/**
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* Initialize the system
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*
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* @param none
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* @return none
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*
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* @brief Setup the microcontroller system.
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* Initialize the System and update the SystemCoreClock variable.
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*/
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extern void SystemInit (void);
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/**
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* Update SystemCoreClock variable
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*
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* @param none
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* @return none
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*
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* @brief Updates the SystemCoreClock with current core Clock
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* retrieved from cpu registers.
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*/
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extern void SystemCoreClockUpdate (void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* SYSTEM_ARMCM4_H */
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