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Erik Tylek Kettenburg
2015-06-23 12:42:35 -07:00
parent bc55c9bb45
commit 6ca6b114d5
3581 changed files with 93 additions and 51 deletions
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64
digistump-sam/system/CMSIS/Device/_Template_Vendor/ReadMe.txt Normal file
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/*****************************************************************************
* @file ReadMe.txt
* @purpose Explanation how to use the Device folder and template files
* @version V2.10
* @date 25. July 2011
*****************************************************************************/
Following directory structure and template files are given:
- <Vendor>
|
+-- <Device>
|
+-- Include
| +- <Device>.h header file
| +- system_Device.h system include file
+-- Source
|
+ Templates
+- system_<Device>.c system source file
|
+-- ARM
| +- startup_<Device>.s startup file for ARMCC
|
+-- GCC
|
+-- IAR
Copy the complete folder including files and replace:
- folder name 'Vendor' with the abbreviation for the device vendor e.g.: NXP.
- folder name 'Device' with your specific device name e.g.: LPC17xx.
- in the filenames 'Device' with your specific device name e.g.: LPC17xx.
The template files contain comments starting with 'ToDo: '
There it is described what you need to do.
The template files contain following placeholder:
<Device>
<Device> should be replaced with your specific device name.
e.g.: LPC17xx
<DeviceInterrupt>
<DeviceInterrupt> should be replaced with a specific device interrupt name.
e.g.: TIM1 for Timer#1 interrupt.
<DeviceAbbreviation>
<DeviceAbbreviation> should be replaced with a dedicated device family
abbreviation (e.g.: LPC for LPC17xx device family)
Cortex-M#
Cortex-M# can be replaced with the specific Cortex-M number
e.g.: Cortex-M3
Note:
Template files (i.e. startup_Device.s, system_Device.c) are application
specific and therefore expected to be copied into the application project
folder prior to use!

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/**************************************************************************//**
* @file <Device>.h
* @brief CMSIS Cortex-M# Core Peripheral Access Layer Header File
* for the Device Series ...
* @version V2.10
* @date 20. July 2011
*
* @note
* Copyright (C) 2010-2011 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef <Device>_H /* ToDo: replace '<Device>' with your device name */
#define <Device>_H
#ifdef __cplusplus
extern "C" {
#endif
/* ToDo: replace '<Device>' with your device name; add your doxyGen comment */
/** @addtogroup <Device>_Definitions <Device> Definitions
This file defines all structures and symbols for <Device>:
- registers and bitfields
- peripheral base address
- peripheral ID
- Peripheral definitions
@{
*/
/******************************************************************************/
/* Processor and Core Peripherals */
/******************************************************************************/
/** @addtogroup <Device>_CMSIS Device CMSIS Definitions
Configuration of the Cortex-M# Processor and Core Peripherals
@{
*/
/*
* ==========================================================================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
typedef enum IRQn
{
/****** Cortex-M# Processor Exceptions Numbers ***************************************************/
/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Hard Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M3 / Cortex-M4 device */
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
/****** Device Specific Interrupt Numbers ********************************************************/
/* ToDo: add here your device specific external interrupt numbers
according the interrupt handlers defined in startup_Device.s
eg.: Interrupt for Timer#1 TIM1_IRQHandler -> TIM1_IRQn */
<DeviceInterrupt>_IRQn = 0, /*!< Device Interrupt */
} IRQn_Type;
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/* Configuration of the Cortex-M# Processor and Core Peripherals */
/* ToDo: set the defines according your Device */
/* ToDo: define the correct core revision
__CM0_REV if your device is a CORTEX-M0 device
__CM3_REV if your device is a CORTEX-M3 device
__CM4_REV if your device is a CORTEX-M4 device */
#define __CM#_REV 0x0201 /*!< Core Revision r2p1 */
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __MPU_PRESENT 1 /*!< MPU present or not */
/* ToDo: define __FPU_PRESENT if your devise is a CORTEX-M4 */
#define __FPU_PRESENT /*!< FPU present or not */
/*@}*/ /* end of group <Device>_CMSIS */
/* ToDo: include the correct core_cm#.h file
core_cm0.h if your device is a CORTEX-M0 device
core_cm3.h if your device is a CORTEX-M3 device
core_cm4.h if your device is a CORTEX-M4 device */
#include <core_cm#.h> /* Cortex-M# processor and core peripherals */
/* ToDo: include your system_<Device>.h file
replace '<Device>' with your device name */
#include "system_<Device>.h" /* <Device> System include file */
/******************************************************************************/
/* Device Specific Peripheral registers structures */
/******************************************************************************/
/** @addtogroup <Device>_Peripherals <Device> Peripherals
<Device> Device Specific Peripheral registers structures
@{
*/
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/* ToDo: add here your device specific peripheral access structure typedefs
following is an example for a timer */
/*------------- 16-bit Timer/Event Counter (TMR) -----------------------------*/
/** @addtogroup <Device>_TMR <Device> 16-bit Timer/Event Counter (TMR)
@{
*/
typedef struct
{
__IO uint32_t EN; /*!< Offset: 0x0000 Timer Enable Register */
__IO uint32_t RUN; /*!< Offset: 0x0004 Timer RUN Register */
__IO uint32_t CR; /*!< Offset: 0x0008 Timer Control Register */
__IO uint32_t MOD; /*!< Offset: 0x000C Timer Mode Register */
uint32_t RESERVED0[1];
__IO uint32_t ST; /*!< Offset: 0x0014 Timer Status Register */
__IO uint32_t IM; /*!< Offset: 0x0018 Interrupt Mask Register */
__IO uint32_t UC; /*!< Offset: 0x001C Timer Up Counter Register */
__IO uint32_t RG0 /*!< Offset: 0x0020 Timer Register */
uint32_t RESERVED1[2];
__IO uint32_t CP; /*!< Offset: 0x002C Capture register */
} <DeviceAbbreviation>_TMR_TypeDef;
/*@}*/ /* end of group <Device>_TMR */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/*@}*/ /* end of group <Device>_Peripherals */
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
/* ToDo: add here your device peripherals base addresses
following is an example for timer */
/** @addtogroup <Device>_MemoryMap <Device> Memory Mapping
@{
*/
/* Peripheral and SRAM base address */
#define <DeviceAbbreviation>_FLASH_BASE (0x00000000UL) /*!< (FLASH ) Base Address */
#define <DeviceAbbreviation>_SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */
#define <DeviceAbbreviation>_PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
/* Peripheral memory map */
#define <DeviceAbbreviation>TIM0_BASE (<DeviceAbbreviation>_PERIPH_BASE) /*!< (Timer0 ) Base Address */
#define <DeviceAbbreviation>TIM1_BASE (<DeviceAbbreviation>_PERIPH_BASE + 0x0800) /*!< (Timer1 ) Base Address */
#define <DeviceAbbreviation>TIM2_BASE (<DeviceAbbreviation>_PERIPH_BASE + 0x1000) /*!< (Timer2 ) Base Address */
/*@}*/ /* end of group <Device>_MemoryMap */
/******************************************************************************/
/* Peripheral declaration */
/******************************************************************************/
/* ToDo: add here your device peripherals pointer definitions
following is an example for timer */
/** @addtogroup <Device>_PeripheralDecl <Device> Peripheral Declaration
@{
*/
#define <DeviceAbbreviation>_TIM0 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
#define <DeviceAbbreviation>_TIM1 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
#define <DeviceAbbreviation>_TIM2 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
/*@}*/ /* end of group <Device>_PeripheralDecl */
/*@}*/ /* end of group <Device>_Definitions */
#ifdef __cplusplus
}
#endif
#endif /* <Device>_H */

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/**************************************************************************//**
* @file system_<Device>.h
* @brief CMSIS Cortex-M# Device Peripheral Access Layer Header File
* for the Device Series ...
* @version V2.10
* @date 20. July 2011
*
* @note
* Copyright (C) 2010-2011 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef SYSTEM_<Device>_H /* ToDo: replace '<Device>' with your device name */
#define SYSTEM_<Device>_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_<Device>_H */

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;/*****************************************************************************
; * @file: startup_<Device>.s
; * @purpose: CMSIS Cortex-M# Core Device Startup File for the
; * Device <Device>
; * @version: V2.10
; * @date: 20. July 2011
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; * Copyright (C) 2010 ARM Limited. All rights reserved.
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; *****************************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; ToDo: Add here the vectors for the device specific external interrupts handler
DCD <DeviceInterrupt>_IRQHandler ; 0: Default
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler\
PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
; ToDo: Add here the export definition for the device specific external interrupts handler
EXPORT <DeviceInterrupt>_IRQHandler [WEAK]
; ToDo: Add here the names for the device specific external interrupts handler
<DeviceInterrupt>_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

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/**************************************************************************//**
* @file system_<Device>.c
* @brief CMSIS Cortex-M# Device Peripheral Access Layer Source File
* for the Device Series ...
* @version V2.10
* @date 20. July 2011
*
* @note
* Copyright (C) 2010-2011 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
#include "<Device>.h"
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
/* ToDo: add here your necessary defines for device initialization
following is an example for different system frequencies */
#define __HSI ( 6000000UL)
#define __XTAL (12000000UL) /* Oscillator frequency */
#define __SYS_OSC_CLK ( ___HSI) /* Main oscillator frequency */
#define __SYSTEM_CLOCK (4*__XTAL)
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
/* ToDo: initialize SystemCoreClock with the system core clock frequency value
achieved after system intitialization.
This means system core clock frequency after call to SystemInit() */
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
/* ToDo: add code to calculate the system frequency based upon the current
register settings.
This function can be used to retrieve the system core clock frequeny
after user changed register sittings. */
SystemCoreClock = __SYSTEM_CLOCK;
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
/* ToDo: add code to initialize the system
do not use global variables because this function is called before
reaching pre-main. RW section maybe overwritten afterwards. */
SystemCoreClock = __SYSTEM_CLOCK;
}