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Erik Tylek Kettenburg
210
digistump-sam/system/libsam/include/ssc.h
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210
digistump-sam/system/libsam/include/ssc.h
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/**
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* \file
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*
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* \brief Synchronous Serial Controller (SSC) driver for SAM.
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*
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* Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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#ifndef SSC_H_INCLUDED
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#define SSC_H_INCLUDED
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#include "../chip.h"
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/// @cond 0
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/**INDENT-OFF**/
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**INDENT-ON**/
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/// @endcond
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//! Receive stop selection.
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#define SSC_RX_STOP_COMPARE_0 0
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#define SSC_RX_STOP_COMPARE_0_1 1
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//! Compare register ID.
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#define COMPARE_ID0 0
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#define COMPARE_ID1 1
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//! SSC module default timeout. */
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#define SSC_DEFAULT_TIMEOUT 10000
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//! \brief SSC driver return codes.
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enum ssc_return_code {
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SSC_RC_OK = 0, //!< OK
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SSC_RC_YES = 0, //!< Yes
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SSC_RC_NO = 1, //!< No
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SSC_RC_ERROR = 1, //!< General error
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SSC_RC_INVALID = 0xFFFFFFFF //!< Parameter invalid
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};
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//! Data frame structure.
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typedef struct {
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//! Data bits length per transfer, should be 0 to 31.
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uint32_t ul_datlen;
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//! Bit sequence LSBF or MSBF.
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//! For receiver configuration, SSC_RFMR_MSBF or 0.
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//! For transmitter configuration, SSC_TFMR_MSBF or 0.
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uint32_t ul_msbf;
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//! Data number per frame, should be 0 to 15.
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uint32_t ul_datnb;
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//! Frame Sync. length should be 0 to 15.
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uint32_t ul_fslen;
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//! Frame Sync. length extension field, should be 0 to 15.
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uint32_t ul_fslen_ext;
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//! Frame Sync. output selection.
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//! For receiver configuration, one of SSC_RFMR_FSOS_NONE, SSC_RFMR_FSOS_NEGATIVE, SSC_RFMR_FSOS_POSITIVE,
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//! SSC_RFMR_FSOS_LOW, SSC_RFMR_FSOS_HIGH or SSC_RFMR_FSOS_TOGGLING.
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//! For transmitter configuration, one of SSC_TFMR_FSOS_NONE, SSC_TFMR_FSOS_NEGATIVE, SSC_TFMR_FSOS_POSITIVE
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//! SSC_TFMR_FSOS_LOW, SSC_TFMR_FSOS_HIGH, SSC_TFMR_FSOS_TOGGLING,
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uint32_t ul_fsos;
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//! Frame Sync. edge detection.
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//! For receiver configuration, SSC_RFMR_FSEDGE_POSITIVE or SSC_RFMR_FSEDGE_NEGATIVE.
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//! For transmitter configuration, SSC_TFMR_FSEDGE_POSITIVE or SSC_TFMR_FSEDGE_NEGATIVE.
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uint32_t ul_fsedge;
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} data_frame_opt_t;
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//! Clock mode structure.
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typedef struct {
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//! Communication clock selection.
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//! For receiver configuration, one of SSC_RCMR_CKS_MCK, SSC_RCMR_CKS_TK or SSC_RCMR_CKS_RK.
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//! For transmitter configuration, one of SSC_TCMR_CKS_MCK, SSC_TCMR_CKS_TK or SSC_TCMR_CKS_RK.
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uint32_t ul_cks;
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//! Communication clock output mode selection.
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//! For receiver configuration, one of SSC_RCMR_CKO_NONE, SSC_RCMR_CKO_CONTINUOUS or SSC_RCMR_CKO_TRANSFER.
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//! For transmitter configuration, one of SSC_TCMR_CKO_NONE, SSC_TCMR_CKO_CONTINUOUS or SSC_TCMR_CKO_TRANSFER.
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uint32_t ul_cko;
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//! Communication clock inversion.
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//! For receiver configuration, SSC_RCMR_CKI or 0.
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//! For transmitter configuration, SSC_TCMR_CKI or 0.
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uint32_t ul_cki;
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//! Communication clock gating selection.
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//! For receiver configuration, one of SSC_RCMR_CKG_NONE, SSC_RCMR_CKG_CONTINUOUS and SSC_RCMR_CKG_TRANSFER.
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//! For transmitter configuration, one of SSC_TCMR_CKG_NONE, SSC_TCMR_CKG_CONTINUOUS and SSC_TCMR_CKG_TRANSFER.
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uint32_t ul_ckg;
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//! Period divider selection, should be 0 to 255.
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uint32_t ul_period;
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//! Communication start delay, should be 0 to 255.
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uint32_t ul_sttdly;
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//! Communication start selection.
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//! For receiver configuration, one of SSC_RCMR_START_CONTINUOUS, SSC_RCMR_START_TRANSMIT, SSC_RCMR_START_RF_LOW,
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//! SSC_RCMR_START_RF_HIGH, SSC_RCMR_START_RF_FALLING, SSC_RCMR_START_RF_RISING, SSC_RCMR_START_RF_LEVEL,
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//! SSC_RCMR_START_RF_EDGE or SSC_RCMR_START_CMP_0.
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//! For transmitter configuration, one of SSC_TCMR_START_CONTINUOUS, SSC_TCMR_START_TRANSMIT, SSC_TCMR_START_RF_LOW,
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//! SSC_TCMR_START_RF_HIGH, SSC_TCMR_START_RF_FALLING, SSC_TCMR_START_RF_RISING, SSC_TCMR_START_RF_LEVEL,
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//! SSC_TCMR_START_RF_EDGE or SSC_TCMR_START_CMP_0.
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uint32_t ul_start_sel;
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} clock_opt_t;
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//! SSC working role in I2S mode.
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#define SSC_I2S_MASTER_OUT (1 << 0) //! Working mode for transmitter as master.
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#define SSC_I2S_MASTER_IN (1 << 1) //! Working mode for receiver as master.
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#define SSC_I2S_SLAVE_OUT (1 << 2) //! Working mode for transmitter as slave.
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#define SSC_I2S_SLAVE_IN (1 << 3) //! Working mode for receiver as slave.
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//! Bit for SSC Audio channel left.
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#define SSC_AUDIO_CH_LEFT (1 << 0)
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//! Bit for SSC Audio channel right.
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#define SSC_AUDIO_CH_RIGHT (1 << 1)
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//! SSC Audio Channel modes.
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enum {
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//! Mono, left channel enabled.
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SSC_AUDIO_MONO_LEFT = (SSC_AUDIO_CH_LEFT),
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//! Mono, right channel enabled.
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SSC_AUDIO_MONO_RIGHT = (SSC_AUDIO_CH_RIGHT),
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//! Stereo, two channels.
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SSC_AUDIO_STERO = (SSC_AUDIO_CH_LEFT | SSC_AUDIO_CH_RIGHT)
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};
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uint32_t ssc_set_clock_divider(Ssc *p_ssc, uint32_t ul_bitclock, uint32_t ul_mck);
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void ssc_i2s_set_transmitter(Ssc *p_ssc, uint32_t ul_mode,
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uint32_t ul_cks, uint32_t ul_ch_mode, uint32_t ul_datlen);
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void ssc_i2s_set_receiver(Ssc *p_ssc, uint32_t ul_mode,
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uint32_t ul_cks, uint32_t ul_ch_mode, uint32_t ul_datlen);
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void ssc_reset(Ssc *p_ssc);
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void ssc_enable_rx(Ssc *p_ssc);
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void ssc_disable_rx(Ssc *p_ssc);
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void ssc_enable_tx(Ssc *p_ssc);
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void ssc_disable_tx(Ssc *p_ssc);
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void ssc_set_normal_mode(Ssc *p_ssc);
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void ssc_set_loop_mode(Ssc *p_ssc);
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void ssc_set_rx_stop_selection(Ssc *p_ssc, uint32_t ul_sel);
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void ssc_set_td_default_level(Ssc *p_ssc, uint32_t ul_level);
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void ssc_enable_tx_frame_sync_data(Ssc *p_ssc);
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void ssc_disable_tx_frame_sync_data(Ssc *p_ssc);
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void ssc_set_receiver(Ssc *p_ssc, clock_opt_t *p_rx_clk_opt, data_frame_opt_t *p_rx_data_frame);
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void ssc_set_transmitter(Ssc *p_ssc, clock_opt_t *p_tx_clk_opt, data_frame_opt_t *p_tx_data_frame);
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void ssc_set_rx_compare(Ssc *p_ssc, uint32_t ul_id, uint32_t ul_value);
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uint32_t ssc_get_rx_compare(Ssc *p_ssc, uint32_t ul_id);
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void ssc_enable_interrupt(Ssc *p_ssc, uint32_t ul_sources);
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void ssc_disable_interrupt(Ssc *p_ssc, uint32_t ul_sources);
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uint32_t ssc_get_interrupt_mask(Ssc *p_ssc);
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uint32_t ssc_get_status(Ssc *p_ssc);
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uint32_t ssc_is_tx_ready(Ssc *p_ssc);
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uint32_t ssc_is_tx_empty(Ssc *p_ssc);
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uint32_t ssc_is_rx_ready(Ssc *p_ssc);
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uint32_t ssc_is_tx_enabled(Ssc *p_ssc);
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uint32_t ssc_is_rx_enabled(Ssc *p_ssc);
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#if (defined _SAM3S_) || (defined _SAM4S_)
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uint32_t ssc_is_rx_buf_end(Ssc *p_ssc);
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uint32_t ssc_is_tx_buf_end(Ssc *p_ssc);
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uint32_t ssc_is_rx_buf_full(Ssc *p_ssc);
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uint32_t ssc_is_tx_buf_empty(Ssc *p_ssc);
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Pdc *ssc_get_pdc_base(Ssc *p_ssc);
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#endif
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uint32_t ssc_write(Ssc *p_ssc, uint32_t ul_frame);
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uint32_t ssc_read(Ssc *p_ssc, uint32_t *ul_data);
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void ssc_write_sync_data(Ssc *p_ssc, uint32_t ul_frame);
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uint32_t ssc_read_sync_data(Ssc *p_ssc);
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#if ((defined _SAM3XA_) || (defined _SAM3U_))
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void *ssc_get_tx_access(Ssc *p_ssc);
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void *ssc_get_rx_access(Ssc *p_ssc);
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#endif
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void ssc_set_writeprotect(Ssc *p_ssc, uint32_t ul_enable);
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uint32_t ssc_get_writeprotect_status(Ssc *p_ssc);
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/// @cond 0
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/**INDENT-OFF**/
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#ifdef __cplusplus
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}
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#endif
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/**INDENT-ON**/
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/// @endcond
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#endif /* SSC_H_INCLUDED */
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