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Erik Tylek Kettenburg
334
digistump-sam/system/libsam/source/uotghs_device.c
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334
digistump-sam/system/libsam/source/uotghs_device.c
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/* ----------------------------------------------------------------------------
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* SAM Software Package License
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* ----------------------------------------------------------------------------
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* Copyright (c) 2011-2012, Atmel Corporation
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following condition is met:
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*
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* - Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the disclaimer below.
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*
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* Atmel's name may not be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* ----------------------------------------------------------------------------
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*/
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#include "chip.h"
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#include <stdio.h>
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#if SAM3XA_SERIES
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//#define TRACE_UOTGHS_DEVICE(x) x
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#define TRACE_UOTGHS_DEVICE(x)
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extern void (*gpf_isr)(void);
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static volatile uint32_t ul_send_fifo_ptr[MAX_ENDPOINTS];
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static volatile uint32_t ul_recv_fifo_ptr[MAX_ENDPOINTS];
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void UDD_SetStack(void (*pf_isr)(void))
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{
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gpf_isr = pf_isr;
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}
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uint32_t UDD_Init(void)
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{
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uint32_t i;
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for (i = 0; i < MAX_ENDPOINTS; ++i)
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{
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ul_send_fifo_ptr[i] = 0;
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ul_recv_fifo_ptr[i] = 0;
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}
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// Enables the USB Clock
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pmc_enable_periph_clk(ID_UOTGHS);
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pmc_enable_upll_clock();
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pmc_switch_udpck_to_upllck(0); // div=0+1
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pmc_enable_udpck();
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// Configure interrupts
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NVIC_SetPriority((IRQn_Type) ID_UOTGHS, 0UL);
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NVIC_EnableIRQ((IRQn_Type) ID_UOTGHS);
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// Always authorize asynchrone USB interrupts to exit from sleep mode
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// for SAM3 USB wake up device except BACKUP mode
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//pmc_set_fast_startup_input(PMC_FSMR_USBAL);
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// ID pin not used then force device mode
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otg_disable_id_pin();
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otg_force_device_mode();
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// Enable USB hardware
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otg_disable_pad();
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otg_enable_pad();
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otg_enable();
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otg_unfreeze_clock();
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// Check USB clock
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//while (!Is_otg_clock_usable())
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// ;
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// Enable High Speed
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udd_low_speed_disable();
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udd_high_speed_enable();
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//otg_ack_vbus_transition();
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// Force Vbus interrupt in case of Vbus always with a high level
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// This is possible with a short timing between a Host mode stop/start.
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/*if (Is_otg_vbus_high()) {
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otg_raise_vbus_transition();
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}
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otg_enable_vbus_interrupt();*/
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otg_freeze_clock();
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return 0UL ;
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}
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void UDD_Attach(void)
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{
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irqflags_t flags = cpu_irq_save();
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TRACE_UOTGHS_DEVICE(printf("=> UDD_Attach\r\n");)
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otg_unfreeze_clock();
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// Check USB clock because the source can be a PLL
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while (!Is_otg_clock_usable());
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// Authorize attach if Vbus is present
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udd_attach_device();
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// Enable USB line events
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udd_enable_reset_interrupt();
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// udd_enable_sof_interrupt();
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cpu_irq_restore(flags);
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}
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void UDD_Detach(void)
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{
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TRACE_UOTGHS_DEVICE(printf("=> UDD_Detach\r\n");)
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UOTGHS->UOTGHS_DEVCTRL |= UOTGHS_DEVCTRL_DETACH;
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}
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void UDD_InitEP( uint32_t ul_ep_nb, uint32_t ul_ep_cfg )
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{
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ul_ep_nb = ul_ep_nb & 0xF; // EP range is 0..9, hence mask is 0xF.
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TRACE_UOTGHS_DEVICE(printf("=> UDD_InitEP : init EP %lu\r\n", ul_ep_nb);)
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// Configure EP
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UOTGHS->UOTGHS_DEVEPTCFG[ul_ep_nb] = ul_ep_cfg;
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// Enable EP
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udd_enable_endpoint(ul_ep_nb);
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if (!Is_udd_endpoint_configured(ul_ep_nb)) {
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TRACE_UOTGHS_DEVICE(printf("=> UDD_InitEP : ERROR FAILED TO INIT EP %lu\r\n", ul_ep_nb);)
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while(1);
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}
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}
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void UDD_InitEndpoints(const uint32_t* eps_table, const uint32_t ul_eps_table_size)
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{
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uint32_t ul_ep_nb ;
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for (ul_ep_nb = 1; ul_ep_nb < ul_eps_table_size; ul_ep_nb++)
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{
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// Configure EP
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UOTGHS->UOTGHS_DEVEPTCFG[ul_ep_nb] = eps_table[ul_ep_nb];
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// Enable EP
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udd_enable_endpoint(ul_ep_nb);
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if (!Is_udd_endpoint_configured(ul_ep_nb)) {
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TRACE_UOTGHS_DEVICE(printf("=> UDD_InitEP : ERROR FAILED TO INIT EP %lu\r\n", ul_ep_nb);)
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while(1);
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}
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}
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}
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// Wait until ready to accept IN packet.
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void UDD_WaitIN(void)
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{
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while (!(UOTGHS->UOTGHS_DEVEPTISR[EP0] & UOTGHS_DEVEPTISR_TXINI))
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;
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}
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void UDD_WaitOUT(void)
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{
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while (!(UOTGHS->UOTGHS_DEVEPTISR[EP0] & UOTGHS_DEVEPTISR_RXOUTI))
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;
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}
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// Send packet.
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void UDD_ClearIN(void)
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{
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TRACE_UOTGHS_DEVICE(printf("=> UDD_ClearIN: sent %lu bytes\r\n", ul_send_fifo_ptr[EP0]);)
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UOTGHS->UOTGHS_DEVEPTICR[EP0] = UOTGHS_DEVEPTICR_TXINIC;
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ul_send_fifo_ptr[EP0] = 0;
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}
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void UDD_ClearOUT(void)
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{
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UOTGHS->UOTGHS_DEVEPTICR[EP0] = UOTGHS_DEVEPTICR_RXOUTIC;
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ul_recv_fifo_ptr[EP0] = 0;
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}
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// Wait for IN FIFO to be ready to accept data or OUT FIFO to receive data.
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// Return true if new IN FIFO buffer available.
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uint32_t UDD_WaitForINOrOUT(void)
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{
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while (!(UOTGHS->UOTGHS_DEVEPTISR[EP0] & (UOTGHS_DEVEPTISR_TXINI | UOTGHS_DEVEPTISR_RXOUTI)))
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;
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return ((UOTGHS->UOTGHS_DEVEPTISR[EP0] & UOTGHS_DEVEPTISR_RXOUTI) == 0);
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}
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uint32_t UDD_ReceivedSetupInt(void)
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{
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return UOTGHS->UOTGHS_DEVEPTISR[EP0] & UOTGHS_DEVEPTISR_RXSTPI;
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}
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void UDD_ClearSetupInt(void)
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{
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UOTGHS->UOTGHS_DEVEPTICR[EP0] = (UOTGHS_DEVEPTICR_RXSTPIC);
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}
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uint32_t UDD_Send(uint32_t ep, const void* data, uint32_t len)
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{
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const uint8_t *ptr_src = data;
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uint8_t *ptr_dest = (uint8_t *) &udd_get_endpoint_fifo_access8(ep);
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uint32_t i;
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TRACE_UOTGHS_DEVICE(printf("=> UDD_Send (1): ep=%lu ul_send_fifo_ptr=%lu len=%lu\r\n", ep, ul_send_fifo_ptr[ep], len);)
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while( UOTGHS_DEVEPTISR_TXINI != (UOTGHS->UOTGHS_DEVEPTISR[ep] & UOTGHS_DEVEPTISR_TXINI )) {}
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if (ep == EP0)
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{
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if (ul_send_fifo_ptr[ep] + len > EP0_SIZE)
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len = EP0_SIZE - ul_send_fifo_ptr[ep];
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}
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else
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{
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ul_send_fifo_ptr[ep] = 0;
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}
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for (i = 0, ptr_dest += ul_send_fifo_ptr[ep]; i < len; ++i)
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*ptr_dest++ = *ptr_src++;
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ul_send_fifo_ptr[ep] += i;
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if (ep == EP0)
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{
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TRACE_UOTGHS_DEVICE(printf("=> UDD_Send (2): ep=%lu ptr_dest=%lu maxlen=%d\r\n", ep, ul_send_fifo_ptr[ep], EP0_SIZE);)
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if (ul_send_fifo_ptr[ep] == EP0_SIZE)
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{
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UDD_ClearIN(); // Fifo is full, release this packet // UOTGHS->UOTGHS_DEVEPTICR[EP0] = UOTGHS_DEVEPTICR_TXINIC;
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}
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}
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else
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{
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UOTGHS->UOTGHS_DEVEPTICR[ep] = UOTGHS_DEVEPTICR_TXINIC;
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UOTGHS->UOTGHS_DEVEPTIDR[ep] = UOTGHS_DEVEPTIDR_FIFOCONC;
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}
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return len;
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}
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void UDD_Send8(uint32_t ep, uint8_t data )
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{
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uint8_t *ptr_dest = (uint8_t *) &udd_get_endpoint_fifo_access8(ep);
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TRACE_UOTGHS_DEVICE(printf("=> UDD_Send8 : ul_send_fifo_ptr=%lu data=0x%x\r\n", ul_send_fifo_ptr[ep], data);)
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ptr_dest[ul_send_fifo_ptr[ep]] = data;
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ul_send_fifo_ptr[ep] += 1;
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}
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uint8_t UDD_Recv8(uint32_t ep)
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{
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uint8_t *ptr_dest = (uint8_t *) &udd_get_endpoint_fifo_access8(ep);
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uint8_t data = ptr_dest[ul_recv_fifo_ptr[ep]];
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TRACE_UOTGHS_DEVICE(printf("=> UDD_Recv8 : ul_recv_fifo_ptr=%lu\r\n", ul_recv_fifo_ptr[ep]);)
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ul_recv_fifo_ptr[ep] += 1;
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return data;
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}
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void UDD_Recv(uint32_t ep, uint8_t* data, uint32_t len)
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{
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uint8_t *ptr_src = (uint8_t *) &udd_get_endpoint_fifo_access8(ep);
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uint8_t *ptr_dest = data;
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uint32_t i;
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for (i = 0, ptr_src += ul_recv_fifo_ptr[ep]; i < len; ++i)
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*ptr_dest++ = *ptr_src++;
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ul_recv_fifo_ptr[ep] += i;
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}
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void UDD_Stall(void)
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{
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UOTGHS->UOTGHS_DEVEPT = (UOTGHS_DEVEPT_EPEN0 << EP0);
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UOTGHS->UOTGHS_DEVEPTIER[EP0] = UOTGHS_DEVEPTIER_STALLRQS;
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}
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uint32_t UDD_FifoByteCount(uint32_t ep)
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{
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return ((UOTGHS->UOTGHS_DEVEPTISR[ep] & UOTGHS_DEVEPTISR_BYCT_Msk) >> UOTGHS_DEVEPTISR_BYCT_Pos);
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}
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void UDD_ReleaseRX(uint32_t ep)
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{
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TRACE_UOTGHS_DEVICE(puts("=> UDD_ReleaseRX\r\n");)
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// UOTGHS->UOTGHS_DEVEPTICR[ep] = (UOTGHS_DEVEPTICR_NAKOUTIC | UOTGHS_DEVEPTICR_RXOUTIC);
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UOTGHS->UOTGHS_DEVEPTICR[ep] = UOTGHS_DEVEPTICR_RXOUTIC;
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UOTGHS->UOTGHS_DEVEPTIDR[ep] = UOTGHS_DEVEPTIDR_FIFOCONC;
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ul_recv_fifo_ptr[ep] = 0;
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}
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void UDD_ReleaseTX(uint32_t ep)
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{
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TRACE_UOTGHS_DEVICE(printf("=> UDD_ReleaseTX ep=%lu\r\n", ep);)
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// UOTGHS->UOTGHS_DEVEPTICR[ep] = (UOTGHS_DEVEPTICR_NAKINIC | UOTGHS_DEVEPTICR_RXOUTIC | UOTGHS_DEVEPTICR_TXINIC);
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UOTGHS->UOTGHS_DEVEPTICR[ep] = UOTGHS_DEVEPTICR_TXINIC;
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UOTGHS->UOTGHS_DEVEPTIDR[ep] = UOTGHS_DEVEPTIDR_FIFOCONC;
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ul_send_fifo_ptr[ep] = 0;
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}
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// Return true if the current bank is not full.
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uint32_t UDD_ReadWriteAllowed(uint32_t ep)
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{
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return (UOTGHS->UOTGHS_DEVEPTISR[ep] & UOTGHS_DEVEPTISR_RWALL);
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}
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void UDD_SetAddress(uint32_t addr)
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{
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TRACE_UOTGHS_DEVICE(printf("=> UDD_SetAddress : setting address to %lu\r\n", addr);)
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udd_configure_address(addr);
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udd_enable_address();
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}
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uint32_t UDD_GetFrameNumber(void)
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{
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return udd_frame_number();
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}
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#endif /* SAM3XA_SERIES */
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