mirror of
https://github.com/digistump/DigistumpArduino.git
synced 2025-04-28 15:49:02 -07:00
298 lines
7.8 KiB
C++
298 lines
7.8 KiB
C++
// This sketch will send a RFM12b packet that is compatible with the Jeelib and can be picked up by a JeeNode running RFM12 demo sketch
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//See http://jeelabs.org/2011/06/09/rf12-packet-format-and-design/
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//for packet design
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#define GROUP 212
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#define HEADER 17
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//433mhz = 1, 868mhz = 2, 915mhz = 3
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#define RF12_FREQ 1
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#define RF12_NOT_CS() PORTB |= _BV(PB3)
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#define RF12_CS() PORTB &= ~_BV(PB3)
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#define MOSI_LOW() PORTB &= ~_BV(PB1)
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#define MISO_LEVEL() (PINB & _BV(PB0))
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#define RF12_TRANSMIT 0xB8
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union
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{
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unsigned char byte;
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struct
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{
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char ATS_RSSI:
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1; //ATS=Antenna tuning circuit detected strong enough RF signal
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//RSSI=The strength of the incoming signal is above the pre-programmed limit
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char FFEM:
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1; //FIFO is empty
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char LBD:
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1; //Low battery detect, the power supply voltage is below the pre-programmed limit
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char EXT:
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1; //Logic level on interrupt pin (pin 16) changed to low (Cleared after Status Read Command)
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char WKUP:
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1; //Wake-up timer overflow (Cleared after Status Read Command )
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char RGUR_FFOV:
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1; //RGUR=TX register under run, register over write (Cleared after Status Read Command )
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//FFOV=RX FIFO overflow (Cleared after Status Read Command )
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char POR:
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1; //Power-on reset (Cleared after Status Read Command )
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char RGIT_FFIT:
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1; //RGIT=TX register is ready to receive the next byte
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//(Can be cleared by Transmitter Register Write Command)
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//FFIT=The number of data bits in the RX FIFO has reached the pre-programmed limit
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//(Can be cleared by any of the FIFO read methods)
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}bits;
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} status_H;
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union
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{
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unsigned char byte;
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struct
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{
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char OFFS:
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4; //Offset value to be added to the value of the frequency control parameter (Four LSB bits)
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char OFFS6:
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1; //MSB of the measured frequency offset (sign of the offset value)
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char ATGL:
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1; //Toggling in each AFC cycle
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char CRL:
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1; //Clock recovery locked
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char DQD:
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1; //Data quality detector output
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}bits;
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} status_L;
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void setup(){
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DDRB = _BV(PB1) | _BV(PB2) | _BV(PB3) | _BV(PB4);
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// MOSI, SCK, SEL
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PORTB = _BV(PB3); // deselect RFM12
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rf12_init();
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}
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//Some extremely dummy packet payload, just to show it works..
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uint8_t data[] = { "TEST" };
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void loop(){
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rf12_cmd(0x82,0x38); //Enable transciever
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rf12_send((uint8_t *)&data, sizeof(data));
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//wait till the next-to-last byte is sent (the last is the dummy)
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while (!rf12_read_status_MSB());
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rf12_cmd(0x82,0x08); //Disable transciever
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delay(3000);
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}
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static void spi_run_clock () {
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USICR = _BV(USIWM0) | _BV(USITC);
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USICR = _BV(USIWM0) | _BV(USITC) | _BV(USICLK);
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USICR = _BV(USIWM0) | _BV(USITC);
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USICR = _BV(USIWM0) | _BV(USITC) | _BV(USICLK);
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USICR = _BV(USIWM0) | _BV(USITC);
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USICR = _BV(USIWM0) | _BV(USITC) | _BV(USICLK);
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USICR = _BV(USIWM0) | _BV(USITC);
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USICR = _BV(USIWM0) | _BV(USITC) | _BV(USICLK);
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USICR = _BV(USIWM0) | _BV(USITC);
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USICR = _BV(USIWM0) | _BV(USITC) | _BV(USICLK);
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USICR = _BV(USIWM0) | _BV(USITC);
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USICR = _BV(USIWM0) | _BV(USITC) | _BV(USICLK);
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USICR = _BV(USIWM0) | _BV(USITC);
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USICR = _BV(USIWM0) | _BV(USITC) | _BV(USICLK);
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USICR = _BV(USIWM0) | _BV(USITC);
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USICR = _BV(USIWM0) | _BV(USITC) | _BV(USICLK);
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}
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void rf12_cmd(uint8_t highbyte, uint8_t lowbyte)
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{
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RF12_CS();
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USIDR = highbyte;
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spi_run_clock();
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USIDR = lowbyte;
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spi_run_clock();
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RF12_NOT_CS();
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}
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void rf12_loop_until_FFIT_RGIT(void)
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{
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do
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{
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rf12_read_status_MSB();
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}
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while (!status_H.bits.RGIT_FFIT);
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}
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/* rf12_read_status_MSB
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RX Mode: FFIT = The number of data bits in the RX FIFO has reached the pre-programmed limit.
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Can be cleared by any of the FIFO read methods
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TX Mode: RGIT = TX register is ready to receive the next byte
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(Can be cleared by Transmitter Register Write Command)
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*/
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uint8_t rf12_read_status_MSB(void)
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{
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RF12_CS();
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MOSI_LOW();
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asm volatile("nop");
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if (MISO_LEVEL())
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status_H.bits.RGIT_FFIT=1;
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else
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status_H.bits.RGIT_FFIT=0;
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RF12_NOT_CS();
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return status_H.bits.RGIT_FFIT;
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}
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void rf12_read_status(void)
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{
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RF12_CS();
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USIDR = 0x00; //Status Read Command
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spi_run_clock();
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status_H.byte = USIDR;
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USIDR = 0x00; //Status Read Command
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spi_run_clock();
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status_L.byte = USIDR;
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RF12_NOT_CS();
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}
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void rf12_TX(uint8_t aByte)
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{
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//FFIT wird gepollt um zu erkennen ob das FIFO TX
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//Register bereit ist.
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//Alternativ ist es auch möglich(wenn verbunden)
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//den Interrupt Ausgang des RF12 zu pollen: while(INT1_LEVEL());
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while (!rf12_read_status_MSB());
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rf12_cmd(RF12_TRANSMIT,aByte);
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}
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#if RF12_RECEIVE_CODE
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uint8_t rf12_RX(void)
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{
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rf12_loop_until_FFIT_RGIT();
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RF12_CS();
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USIDR = 0xB0;
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spi_run_clock();
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USIDR = 0x00;
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spi_run_clock();
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RF12_NOT_CS();
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return USIDR;
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}
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#endif
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static __inline__ uint16_t _crc16_update(uint16_t __crc, uint8_t __data)
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{
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uint8_t __tmp;
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uint16_t __ret;
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__asm__ __volatile__ (
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"eor %A0,%2" "\n\t"
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"mov %1,%A0" "\n\t"
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"swap %1" "\n\t"
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"eor %1,%A0" "\n\t"
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"mov __tmp_reg__,%1" "\n\t"
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"lsr %1" "\n\t"
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"lsr %1" "\n\t"
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"eor %1,__tmp_reg__" "\n\t"
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"mov __tmp_reg__,%1" "\n\t"
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"lsr %1" "\n\t"
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"eor %1,__tmp_reg__" "\n\t"
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"andi %1,0x07" "\n\t"
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"mov __tmp_reg__,%A0" "\n\t"
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"mov %A0,%B0" "\n\t"
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"lsr %1" "\n\t"
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"ror __tmp_reg__" "\n\t"
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"ror %1" "\n\t"
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"mov %B0,__tmp_reg__" "\n\t"
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"eor %A0,%1" "\n\t"
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"lsr __tmp_reg__" "\n\t"
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"ror %1" "\n\t"
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"eor %B0,__tmp_reg__" "\n\t"
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"eor %A0,%1"
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: "=r" (__ret), "=d" (__tmp)
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: "r" (__data), "0" (__crc)
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: "r0"
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);
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return __ret;
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}
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void rf12_send(const uint8_t* buf, uint8_t cnt)
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{
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if (!cnt) return;
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uint16_t chksum=~0;
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//See http://jeelabs.org/2011/06/09/rf12-packet-format-and-design/
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//http://jeelabs.org/2010/12/07/binary-packet-decoding/
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rf12_TX(0xAA); //PREAMBLE
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rf12_TX(0xAA); //PREAMBLE
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rf12_TX(0xAA); //PREAMBLE
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rf12_TX(0x2D); //SYNC HI BYTE
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rf12_TX(GROUP); //SYNC LOW BYTE (group 210)
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chksum = _crc16_update(chksum, GROUP);
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rf12_TX(HEADER); // Header byte
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chksum = _crc16_update(chksum, HEADER);
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rf12_TX(cnt);
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chksum = _crc16_update(chksum, cnt);
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while (cnt--)
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{
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rf12_TX(*buf);
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chksum = _crc16_update(chksum,*buf++);
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}
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rf12_TX(chksum);
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rf12_TX(chksum>>8);
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rf12_TX(0xAA); //dummy byte
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}
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#if RF12_RECEIVE_CODE
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//returns 0 if no data is available
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//returns -1(255) if there is a CRC Error
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//else, returns number of received byte
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uint8_t rf12_read(uint8_t* buf, const uint8_t max)
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{
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uint16_t checksum=~0;
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uint16_t received_checksum;
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uint8_t hdr;
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hdr=rf12_RX();
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checksum = _crc16_update(checksum,hdr);
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uint8_t len;
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len=rf12_RX();
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checksum = _crc16_update(checksum,len);
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uint8_t i=len;
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while (i--)
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{
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*buf=rf12_RX();
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checksum = _crc16_update(checksum,*buf++);
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}
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received_checksum=rf12_RX();
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received_checksum=received_checksum<<8;
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received_checksum |= rf12_RX();
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if (received_checksum==checksum)
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return len;
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else
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return -1;
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}
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#endif
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void rf12_init(void)
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{
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USICR = _BV(USIWM0); // 3-wire, software clock strobe
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rf12_cmd(0x80, 0xC7 | (RF12_868MHZ << 4)); // EL (ena TX), EF (ena RX FIFO), 12.0pF
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rf12_cmd(0xA6,0x40); // 868MHz
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rf12_cmd(0xC6,0x06); // approx 49.2 Kbps, i.e. 10000/29/(1+6) Kbps
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rf12_cmd(0x94,0xA2); // VDI,FAST,134kHz,0dBm,-91dBm
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rf12_cmd(0xC2,0xAC); // AL,!ml,DIG,DQD4
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rf12_cmd(0xCA,0x83); // FIFO8,2-SYNC,!ff,DR
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rf12_cmd(0xCE,0x00 | GROUP); // SYNC=2DXX；
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rf12_cmd(0xC4,0x83); // @PWR,NO RSTRIC,!st,!fi,OE,EN
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rf12_cmd(0x98,0x50); // !mp,90kHz,MAX OUT
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rf12_cmd(0xCC,0x77); // OB1，OB0, LPX,！ddy，DDIT，BW0
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rf12_cmd(0xE0,0x00); // NOT USE
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rf12_cmd(0xC8,0x00); // NOT USE
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rf12_cmd(0xC0,0x40); // 1.66MHz,2.2V
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}
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